1. Field of the Invention
This invention relates to an integrated circuit process and a resulting structure. More particularly, this invention relates to a method of enabling alignment of a wafer in at least one exposure step of an integrated circuit (IC) process after a UV-blocking metal layer is formed over the whole wafer, to an IC process incorporating the step of the above method, and to a wafer structure resulting from a part of the above process.
2. Description of the Related Art
In the fabricating process of an integrated circuit sensitive to UV-light, such as a non-volatile memory operated by carrier injection and removal, a UV-blocking metal layer is usually formed over the whole wafer after the passivation layer covering the upmost metal layer is formed. The openings exposing the bonding pads in the upmost metal layer are formed through the UV-blocking metal layer and the passivation layer.
FIGS. 1A and 1B illustrate a two-photo process in the prior art for defining the openings above the bonding pads of a non-volatile memory after a UV-blocking layer is formed screening the zero alignment mark on the wafer.
Referring to FIG. 1A, a wafer 100 including dies 102 and an edge portion 104 is provided, wherein only one die 102 is shown for simplicity. Each die 102 includes a periphery circuit area 106 and an array area 108, with a circuit of a non-volatile memory and the accompanying dielectric layers 120 thereon. The edge portion 104 is formed with a zero alignment 110 thereon, and is screened in the deposition of any conductive layer to be defined into a portion of the circuit so that only the dielectric layers 120 are formed thereon as a composite dielectric layer. An upmost metal layer, which includes bonding pads 130a within the periphery circuit area 106 and other upmost metal patterns 130b, has been formed on the dielectric layers 120, wherein only one bonding pads 130a is shown for simplicity. A passivation layer 140 has been formed over the whole wafer 100 covering the upmost metal layer, and a UV-blocking metal layer 150 has been formed over the whole passivation layer 140.
In the first stage of the two-photo process, a photoresist layer 160 is formed over the whole wafer 100, and then a portion thereof above the edge portion 104 is exposed and removed in subsequent development. The UV-blocking layer 150 thus exposed is then removed in an etching step 162 making the zero alignment mark 110 under the transparent layers 120 and 140 optically detectable.
After the photoresist layer 160 is removed, a water-resistant layer 170 is formed over the whole wafer 100 covering the remaining UV-blocking metal layer 150a. A photoresist layer 180 is formed over the whole wafer 100 and exposed by a photomask 10 to form an exposed region 180a over each bonding pad 130a. Because the zero alignment mark 110 under the transparent layers 120 and 140 is optically detectable, the wafer 100 can be aligned using an optical method based on the zero alignment mark 110 in the exposure using the photomask 10. After the exposed region 180a is removed in subsequent development, the photoresist layer 180 is used as an etching mask to form an opening through the a water-resistant layer 170, the UV-blocking metal layer 150 and the passivation layer 140 above the bonding pad 130a. 
The above partial removal process for the UV-blocking metal layer 150 as shown in FIG. 1A needs an extra photomask, and the coating, exposure, development and so forth of the photoresist layer consume much time.